{"id":3888,"date":"2020-08-28T07:20:32","date_gmt":"2020-08-28T07:20:32","guid":{"rendered":"http:\/\/www.raymaps.com\/?p=3888"},"modified":"2022-06-03T11:07:47","modified_gmt":"2022-06-03T11:07:47","slug":"phase-lock-loop-explained","status":"publish","type":"post","link":"https:\/\/www.raymaps.com\/index.php\/phase-lock-loop-explained\/","title":{"rendered":"Phase Lock Loop – Explained"},"content":{"rendered":"\n

Phase Lock Loops (PLLs) are an important\ncomponent of communication systems, where they are used for carrier phase and\nfrequency synchronization. They are also used in test and measurement equipment\nsuch as in Signal Generators and Vector Network Analyzers (VNAs) for frequency\nsynthesis. Although not discussed here in detail but PLLs are also quite adept\nat generating multiples of a base frequency e.g. if you have a reference signal\nat 10MHz then a PLL can be used to generate a 100MHz signal (X=10) or even a\n1GHz signal (X=100). In fact, you can also divide the frequency to get low\nfrequency signals. In the first case the feedback frequency is divided by X and\nin the second case the reference or input frequency is divided by X. <\/p>\n\n\n\n\n\n\n\n

All Analog Phase Lock Loops have three\nbasic components; a Mixer, a Low Pass Filter (LPF) and a Voltage Controlled\nOscillator (VCO). The inputs to the Mixer include a reference signal (i\/p\nsignal) and a VCO signal (o\/p signal). In case these are not phase and frequency\nsynchronized an error signal will be generated which will consist of a sinusoid\nthat has a frequency which is the difference of the two frequencies and a\nsinusoid that has a frequency which is the sum of the two frequencies. An LPF\nis then used to remove the high frequency component and the low frequency\ncomponent is used as a control signal by the VCO. As the name suggests the\noutput of the VCO is a signal whose frequency is directly proportional to the\ninput voltage. Higher the difference between input and output frequency greater\nis the value of the error signal. <\/p>\n\n\n\n

There are three main modes of operation of\nPLLs.<\/p>\n\n\n\n

  1. Free running: no input is applied<\/li>
  2. Capture mode: input is applied and output starts tracking it<\/li>
  3. Lock mode: input and output are synchronized in phase and frequency<\/li><\/ol>\n\n\n\n

    Type-1 Phase Lock Loop<\/p>\n\n\n\n

    \"\"
    Block Diagram of Type 1 Phase Lock Loop<\/figcaption><\/figure>\n\n\n\n
    %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Sampled time-domain simulation of an analog Phase Locked Loop (PLL)\n%        (Type-1 with Multiplier, Low-Pass Filter and VCO)\n%\n%                 Adapted from aaronscher.com\n%\n%     The input signal or reference signal is a simple sinusoid. \n%   The output signal is also a sinusoid that tracks the frequency \n%      of the reference signal after a certain start up time.\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\nclear all\nclose all\n\n%Simulatiuon Parameters\nN=2000;\nfc=1e9;       \nphase_ref=0.5;  \nf_VCO=1.1e9;   \nK_VCO=1.0e9;   \nfs=100*fc;         \nfilter_length=100; \n\n% Defining the Filter Coefficients\nfilter_coeff=0.54-0.46*cos(0:2*pi\/filter_length:2*pi);\nfilter_coeff=filter_coeff\/sum(filter_coeff);\n\n% Initialiazing the Signal Vectors\nts=1\/fs; \nt_vec=0:ts:(N-1)*ts; \nref_signal=sin(2*pi*fc*t_vec+phase_ref);\noutput_phase=zeros(1,N);\noutput_signal=zeros(1,N);\nerror_mult=zeros(1,N+filter_length);\n\n% PLL Loop (Multiplier, Filter, VCO)\nfor n=2:N\n    t=(n-2)*ts;\n    error_mult(n+filter_length-1)=ref_signal(n)*output_signal(n-1);\n    error_filtered(n)=sum(error_mult(n-1:n+filter_length-1).*(filter_coeff));\n    output_phase(n)=output_phase(n-1)+2*pi*error_filtered(n)*K_VCO*ts;\n    output_signal(n)=sin(2*pi*f_VCO*t+output_phase(n));\nend\n\n%Plot Error Signal\nplot(t_vec,error_mult(filter_length+1:end),'b');hold on\nplot(t_vec,error_filtered,'r');hold off\ntitle('Error signal')\nxlabel('Time(sec)')\nylabel('Error(V)')\nlegend('Raw Error','Filtered Error')\ngrid on\n<\/pre>\n\n\n\n
    \"\"
    Error Signal of Type-1 PLL<\/figcaption><\/figure>\n\n\n\n
    Type-2 Phase Lock Loop<\/p>\n\n\n\n
    \"\"
    Block Diagram of Type 2 Phase Lock Loop<\/figcaption><\/figure>\n\n\n\n
    %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n% Sampled time-domain simulation of an analog Phase Locked Loop (PLL)\n% Type-2 with Multiplier, Low-Pass Filter, VCO, Gains and Integrator\n%\n%                 Adapted from aaronscher.com\n%\n%     The input signal or reference signal is a simple sinusoid. \n%   The output signal is also a sinusoid that tracks the frequency \n%      of the reference signal after a certain start up time.\n%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%\n\nclear all\nclose all\n\n% Simulation Parameters\nN=2000;\nfc=1e9;       \nphase_ref=0.5;  \nf_VCO=1.1e9;   \nK_VCO=0.5e9;   \nfs=100*fc;         \nfilter_length=100; \nG1=0.5;\nG2=2.0e8; \n\n% Defining the Filter Coefficients\nfilter_coeff=0.54-0.46*cos(0:2*pi\/filter_length:2*pi);\nfilter_coeff=filter_coeff\/sum(filter_coeff);\n\n% Initialiazing the Signal Vectors\nts=1\/fs; \nt_vec=0:ts:(N-1)*ts; \nref_signal=sin(2*pi*fc*t_vec+phase_ref);\noutput_phase=zeros(1,N);\noutput_signal=zeros(1,N);\nbranch1=zeros(1,N);\nbranch2=zeros(1,N); \nerror_mult=zeros(1,N+filter_length);\n\n% PLL Loop (Multiplier, Filter, VCO)\nfor n=2:N\n    t=(n-2)*ts;\n    error_mult(n+filter_length-1)=ref_signal(n)*output_signal(n-1);\n    error_filtered(n)=sum(error_mult(n-1:n+filter_length-1).*(filter_coeff));\n    branch1(n)=G1*error_filtered(n);\n    branch2(n)=branch2(n-1)+G2*error_filtered(n)*ts;\n    PI_error(n)=branch1(n)+branch2(n);\n    output_phase(n)=output_phase(n-1)+2*pi*PI_error(n)*K_VCO*ts;\n    output_signal(n)=sin(2*pi*f_VCO*t+output_phase(n));   \nend\n\n%Plot Error Signal\nplot(t_vec,error_mult(filter_length+1:end),'b');hold on\nplot(t_vec,error_filtered,'r');hold off\ntitle('Error signal')\nxlabel('Time(sec)')\nylabel('Error(V)')\nlegend('Raw Error','Filtered Error')\ngrid on\n<\/pre>\n\n\n\n
    \"\"
    Error Signal of Type-2 PLL<\/figcaption><\/figure>\n\n\n\n
    Type-1 vs Type-2<\/strong><\/p>\n\n\n\n
    We have seen that the filtered error of\nType-2 PLL goes down much more rapidly than Type-1 PLL. But now let us look at\nthe input to the VCO, the control signal to the VCO. This is not the same as\nLPF output as one more stage is added in Type-2 PLL. But before we do an\nanalysis of the results, we must warn you that a PLL is a non-linear system and\nthe results might not always make sense. Some linear models of PLLs do exist\nthat make the analysis simpler. This will be the subject of a future post. <\/p>\n\n\n\n
    If we make K_VCO to be the same for both\nthe PLLs (it was not the same in the above examples) than we can make an apple\nto apple comparison. We set K_VCO to be 1.0e9 for both the cases and then look\nat the VCO control signal. As expected, the VCO control signal settles down\nmuch more quickly in Type-2 than in Type-1. This is the main advantage of\nType-2 PLL, it locks on to the reference much more quickly. <\/p>\n\n\n\n
    Simulation results have shown that capture\nrange of Type-2 PLL is also larger than Type-1 PLL. When the difference in\ninput and output frequency is more than 400MHz the control voltage of Type-1\nPLL keeps oscillating and PLL does not go into lock. One might think that\nreducing the cut-off frequency of the LPF can solve this problem, but this is\nnot the case. According to some references increasing  K_VCO and cutoff frequency of the LPF in fact\nincreases the capture range.<\/p>\n\n\n\n
    To further understand the PLL we need to revisit damped sinusoidal function and its s-domain equivalent. This will be the topic of a future post.   <\/p>\n\n\n\n
    \"\"
    VCO Control Signal Type1 vs Type2<\/figcaption><\/figure>\n\n\n\n
    Note: <\/p>\n\n\n\n
    1. A PLL can also be used as an FM demodulator by taking the output of the loop filter before its fed to the VCO.<\/li>
    2. It is possible for a PLL to have a phase offset between input and output, but when locked, the output frequency must exactly track the input frequency.<\/li>
    3. The type of a PLL refers to the number of poles of the loop transfer function located at the origin. This is controlled by the number of integrators in the loop, VCO being one integrator itself. 
      <\/li>
    4. For the filter coefficients we just used a Hamming window since it works quite well and not everyone has access to Signal Processing toolbox which provides the “fir1” function.<\/li>
    5. For Digital PLLs the mixer is replaced by a XOR gate, which gives a high output whenever the two digital inputs are different. This signal is then passed on to a simple moving average filter the output of which is used to control the VCO. When the two inputs to the XOR gate are perfectly synchronized in phase and frequency the output of the XOR gate is zero.  <\/li><\/ol>\n\n\n\n
      References:<\/p>\n\n\n\n
      http:\/\/www.aaronscher.com\/phase_locked_loop\/matlab_pll.html<\/a><\/p>\n\n\n\n
      https:\/\/www.electronics-notes.com\/articles\/radio\/pll-phase-locked-loop\/tutorial-primer-basics.php<\/a><\/p>\n\n\n\n
      https:\/\/www.analog.com\/en\/analog-dialogue\/articles\/phase-locked-loop-pll-fundamentals.html<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
      Phase Lock Loops (PLLs) are an important component of communication systems, where they are used for carrier phase and frequency synchronization. They are also used in test and measurement equipment such as in Signal Generators and Vector Network Analyzers (VNAs) for frequency synthesis.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[81],"tags":[70,220,228],"class_list":["post-3888","post","type-post","status-publish","format-standard","hentry","category-fundamentals","tag-frequency","tag-phase","tag-pll"],"_links":{"self":[{"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/posts\/3888","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/comments?post=3888"}],"version-history":[{"count":15,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/posts\/3888\/revisions"}],"predecessor-version":[{"id":4271,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/posts\/3888\/revisions\/4271"}],"wp:attachment":[{"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/media?parent=3888"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/categories?post=3888"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.raymaps.com\/index.php\/wp-json\/wp\/v2\/tags?post=3888"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}